1. Field of Invention
The present invention relates to a method for manufacturing a capacitor and an interconnect. More particularly, the present invention relates to a method for manufacturing a capacitor and an interconnect of a mixed-mode circuit.
2. Description of Related Art
A mixed-mode circuit device typically includes a circuit comprising both digital and analog devices in a logic area of a semiconductor chip. The digital devices include inverters, adders, and the analog devices include amplifiers and analog-to-digital converters. Currently, the mixed-mode circuit device comprises a capacitor structure. In the common mixed-mode logic manufacturing process, double polysilicon layers are used as capacitor electrodes. The capacitor with double polysilicon layers as electrodes are called a double polysilicon capacitor (DPC).
FIG. 1 is schematic, cross-sectional view of a conventional double polysilicon capacitor. Conventionally, the method for manufacturing a double polysilicon capacitor comprises the steps of forming a thin oxide layer (not shown) and a polysilicon layer (not shown) on a substrate 100 and an isolation region 116, and then patterning the thin oxide layer and the polysilicon layer to form a polysilicon gate electrode 106 and gate oxide layer 104 of a field effect transistor 110 and to form a bottom electrode 108 of a double polysilicon capacitor 102. The field effect transistor 110 is located on the substrate 100 and the bottom electrode 108 is located on the field oxide layer 116. After that, a dielectric layer (not shown) and a polysilicon layer (not shown) are formed on the substrate 100 and then the dielectric layer and the polysilicon layer are patterned to form a capacitor dielectric layer 112 and an upper electrode 114 of the double polysilicon capacitor 102.
The thickness of the polysilicon layer used to form the bottom electrode 108 is different from that of the polysilicon layer used to form the upper electrode 114, so that the polysilicon layer on the sidewall of the bottom electrode 108 is difficult to remove in the patterning process. The stringer effect easily occurs.
Additionally, in order to increase the conductivity of the bottom electrode 108 and the upper electrode 114, dopants are implanted into the bottom electrode 108 and the upper electrode 114. However, the resistance of the bottom electrode 108 and the upper electrode 114 is still high. Moreover, when the mixed-mode device is operated, the dopants in the capacitor are affected by the supplied voltage to form a depletion region at the interface between the capacitor dielectric layer 112 and the bottom electrode 108 and at the interface between the capacitor dielectric layer 112 and the upper electrode 114. The depletion region is considered an extension of the thickness of the capacitor dielectric layer 112. Nevertheless, the charge storage ability of the capacitor 102 is related to the thickness of the capacitor dielectric layer 112. The charge storage ability of the capacitor worsens as the thickness of the capacitor dielectric layer 112 increases. Therefore, the capacitance of the capacitor 102 is decreased and the operation efficiency of the devices is decreased. Furthermore, the thickness of the depletion region varies with the supplied voltage, that leads to an increase voltage coefficient (1/C, dC/dV) for the capacitor. Hence, the capacitance of the capacitor 102 varies with the supplied voltage and the devices are unstable.
In the analog circuit, the capacitance is used as a converting basis for the time delay (.quadrature., .quadrature.=RC), so that the accuracy capacitance requirement of the analog devices is very critical. Incidentally, the operation efficiency is greatly affected by the increase of the voltage coefficient.
Additionally, the capacitor 102 is a two-dimensional capacitor. The surface of the capacitor 102 is increased to increase the capacitance. However, the increase of the capacitor surface leads to decreased device integration.